5 CLAIMS

• 1. A pulse source circuit for providing a sequence of output pulses wherein, in the absence of a failure in the pulse source circuit, alternate output pulses occur in response to signals of one generator and the remaining output pulses occur in response to signals of another generator and, in the presence of a failure of either one of the generators, all output pulses occur in response to signals of the remaining generator comprising:
• two independent but synchronized generators of repetitive signals;
• a pulse output terminal;
• bistable means for generating control signals at first and second output terminals in response to control signals at a control input terminal;
• first gating means having input terminals connected to said generators and to said first and second output terminals of said bistable means for providing at said pulse output terminal a sequence of pulses in response to output signals of said generators and to said control signals; and
• second gating means having input terminals connected to said generators and to said first and second output terminals of said bistable means for generating signals at said control input terminal for controlling the states of said bistable means in response to output signals of said generators and to said control signals.
• 2. A pulse source circuit in accordance with claim 1 wherein said bistable means comprises a toggle flip-flop.
• 3. A pulse source circuit for providing a sequence of output pulses wherein, in the absence of a failure in the pulse source circuit, alternate output pulses occur in response to signals of one generator and the remaining output pulses occur in response to signals of another generator and, in the presence of a failure of either one of the generators, all output pulses occur in response to signals of the remaining generator comprising:
• first and second independent but synchronized generators of repetitive signals;
• a pulse output terminal;
• bistable means for generating control signals at first and second output terminals responsive to control signals at a control input terminal;
• first gating means having input terminals connected to said generators and to said first output terminal of said bistable means for providing at said pulse output terminal a sequence of pulses in response to output signals of said first generator and for generating signals at said control input terminal of said bistable means for switching the states of said bistable means in response to output signals of said second generator; and
• second gating means having input terminals connected to said generators and to said second output terminal of said bistable means for providing at said pulse output terminal a sequence of pulses in response to output signals of said second generator and for generating signals at said control input terminal of said bistable means for switching the states of said bistable means in response to output signals of said first generator.
• 4. A pulse source circuit in accordance with claim 3 wherein said bistable means comprises a toggle flip-flop.
• 5. A pulse source circuit for maintaining a sequence of pulses in the presence of a failure of one pulse generator whose output signal is either stuck high or stuck low comprising:
• a pulse output terminal;
• two independent but synchronized generators of repetitive signals;
• a toggle flip-flop having a control input terminal and first and second complementary output terminals;
• first and second NAND gates having inputs connected to said first generator;
• third and fourth NAND gates having inputs connected to said second generator;
• said first and third NAND gates also having inputs connected to said first output terminal of said toggle flip-flop and said second and fourth NAND gates also having inputs connected to said second output terminal of said toggle flip-flop;
• a first AND gate having inputs connected to the outputs of said second and third NAND gates and having an output connected to said output terminal; and
• a second AND gate having inputs connected to the outputs of said first and fourth NAND gates and having an output connected to said control input terminal of said toggle flip-flop.