Fairfield University School of Engineering
Syllabus

COURSE:                  EE231L Analog Electronics I Laboratory - Fall, 2014

INSTRUCTOR:        Jeffrey N. Denenberg

Google Voice:  (203) 513-9427

Office:  Bannow 301C, (203) 254-3330

Email:  jeffrey.denenberg@ieee.org

Web: http://doctord.webhop.net/

INSTRUCTOR ASSISTANCE: Mon & Thurs. 5:00 - 6:00 and by phone or email at any time.

CLASS HOURS:  1.25 hours twice a week (Mon & Thurs) starting at 3:30 pm on in Bannow 133.

COURSE DESCRIPTION: 

Students build and test circuits using diodes, bipolar junction transistors, and MOSFETs .They use the principles developed in EE 231 to analyze, build, and test amplifier and oscillator circuits.

PREREQUISITE: EE213L, Analog Electronics Lab I (or equivalent)

CO-REQUISITE: EE 231, “Analog Electronics I” (or equivalent).
 The student should also be able to simulate systems using Multisim (or LTSpice) and MatLab.

COURSE OBJECTIVES AND LEARNING OUTCOMES

Objective

Learning Outcome

Cognitive Level

ABET a-k

1.

Students will design electronic solutions to meet specified requirements.

Students will become proficient at doing electronic design to meet requirements.

Synthesis

a, b, c, d, e, k

2.

Students will use Multisim to simulate their electronic designs.

Students will become proficient at using circuit simulation to test their designs.

Analysis

b, c, k

3.

Students will use Laboratory Instruments and Elvis to debug and test their electronic designs.

Students will become proficient at using laboratory instruments.

Evaluation

b, c, k

4.

Students will write Lab reports on their design experience.

Students will become proficient at describing their circuit designs and methodology.

Evaluation

a, b, c, e, g, k

Lab Manual:  “Laboratory Explorations to Accompany Microelectronic Circuits”, 6th Edition-2014, Vincent C Gaudet & Kenneth C. Smith, ISBN 9780195378733, Oxford University Press

SW:     The student should have access to Multisim and MatLab (Full or Student version)

COURSE REQUIREMENTS

The student is expected to attend all of the scheduled classes if for some reason the student can not make a class the Instructor should be contacted in advance, if possible, to arrange to do and turn in the assigned work and get assignment for following class. The course includes three introductory labs (including one on instrumentation) and 4 Design exercises. The student is expected to turn in all work on time.

BlackBoard

The Blackboard system along with our course web site will be used to manage this course.

CLASS SCHEDULE AND TOPICS

SESSION

 

No.

DATE

TOPIC

References

1a

9/4

Course Intro: Syllabus, Multisim,
Test Instruments, Elvis and Multisym

Multisim Tutorial, Multisim Manual,

Elvis II Manual

2a, 2b

9/8,

9/11

Laboratory 2.1: An Inverting OpAmp*

Lab2-1.pdf
Lab Report Form

3a, 3b

9/15, 9/18

Laboratory 2.4: An Instrumentation Amplifier

Lab2-4.pdf

4a, 4b

9/22, 9/25

Laboratory 4.1: Diode I-V Transfer Curve

Lab4-1.pdf

5a, 5b

9/29, 10/2

Laboratory 4.2: Diode Rectifiers  

Lab4-2.pdf

6a, 6b

10/6, 10/9

Laboratory 4.3: Limiting and Clamping Circuits 

Lab4-3.pdf


7b

10/13, 10/16

Columbus Day – No Class
Laboratory 5.1: NMOS I-V Characteristics

Lab5-1.pdf

Lab5-2.pdf

8a, 8b

10/20, 10/23

Laboratory 5.5: NMOS Common-Source Amp.
DoctorD not here – Finish Lab 5.5

Lab5-5.pdf

9a, 9b

10/27, 10/30

Laboratory 5.12: PMOS Source Follower

Lab5-12.pdf

10a, 10b

11/3, 11/6

Make-up Lab period

 

11a, 11b

11/10, 11/13

Laboratory 6.1: NPN I-V Characteristics

Lab6-1.pdf

Lab6-2.pdf

12a, 12b

11/17, 11/20

Laboratory 6.5: NPN Common-Emitter Amplifier

Lab6-5.pdf

13a

11/24, 11/27

Laboratory 6.12: PNP Emitter Follower

Thanksgiving – No Class

Lab6-12.pdf

14a, 14b

11/30,

 

12/4

Complete Lab 6.12

Laboratory 6.13: NMOS vs. NPN Common‑source/Common-Emitter Amplifier

Lab6-13.pdf

15a, 15b

12/7, 12/11

Complete Lab 6.13

Make-up Lab period

 

 

12/13-12/21

Final Exam Week

 

* All laboratory reports are each due and uploaded to Mentor the following Lab Period
   Our Lab (BNW133) is accessible via your Stag Card if you need extra time to complete your work.

You will find that coming to the lab having done preliminary design work and with working Multisim simulations will allow you to easily complete your work in the allotted lab time.

GRADING

Design Lab Reports (12)

7% each

Lab Team Participation

16%