EE 331 Analog Electronics 2
Course Syllabus (Spring 2017)
Fairfield University School of Engineering

Course Number: EE 331

Course Name: Analog Electronics 2

Time: Tuesdays 9:00am - 11:00am

Course Location: Bannow - 133

Instructor: Jeffrey N. Denenberg

Final Exam: TBD

Office: Bannow - 301C

Hours: Mon, Tues, Thurs, Fri 2:00 – 3:30 pm

Office Phone: 203-254-3330

Google Voice: (203) 513-9427

Email: jeffrey.denenberg@ieee.org

jdenenberg@fairfield.edu

WWW: http://doctord.webhop.net

Course Description:

This advanced course in electronics examines high frequency response of bipolar junction transistor and field-effect transistor amplifiers using hybrid two-port active device models. Students consider the effect of feedback and frequency compensation techniques on the amplifier response and study a variety of analog circuits with respect to their analysis and applications, including active filters, oscillators, waveform generation and shaping, voltage regulator, and communication circuits. The course introduces basic power electronics device components. 

This spring EE331 is a “special projects” course and includes EE331L as an integral part.  All Exams are “take home”

Prerequisites:     EE221, EE231
Co-requisite:       EE331L

Objectives and Outcomes

No.

Outcome

Cognitive Level

ABET a-k

1

Students will understand the role and importance of electronics in the modern world.

Knowledge, Comprehension

f, h, i, j

2

Students will be able to analyze and design biasing circuits for amplifiers and relate it

to the given requirements.

Analysis,
Synthesis

a, c. e, k

3

Students will be able to design BJT and FET circuits for  applications to meet performance requirements

Synthesis

a, c. e, k

4

Students will develop large and small signal AC equivalent circuits to help in analysis of the amplifier circuits both for BJT and FET

Analysis

a, c. e, k

5

Students will apply diodes in to provide a variety of functions

operation and basic design steps

Analysis,
Synthesis

a, c. e, k

6

Students will apply Op Amp concepts and basic design of Op Amps

Application,

Synthesis

a, c. e, k


Textbook:

“Microelectronic Circuits”, 2nd Edition (2010), Sedra/Smith, ISBN 0-19-532303-3, OUP

Reference:

 “Schaum's Outline of Electronic Devices and Circuits”, 2nd Edition (2002), Jimmie J. Cathey, ISBN 0-07-136270-3

Performance Indicators and grading:

Two written exams will be given at approximately equal intervals during the term as outlined in the syllabus. The exams will be open book, open notes.

Semester Exams (2)

40%

Final Exam

20%

Homework/Class Participation

20%

Laboratory performance

20%

Exam grading:

The purpose of the exam is to convey your understand the material; therefore, it is important that you show your work.  Even if you feel that the solution to a problem is obvious; you must still explain why it is obvious.  Furthermore; if you are asked to solve

a problem using a given technique; then please use that technique; otherwise, I have no way to judge your understanding of the technique being tested.

Homework policy:

The purpose of homework:

A: To give student practice.

B: To give professor feedback.

Homework will be collected and graded.

Grade is based more on honest effort than correct answers.

Homework is due the next class after it is assigned (except when specified). This two week homework cycle gives an intervening class where students can ask questions. Late homework assignments are not accepted.  If you know you have a conflict, please make arrangements ahead for time.

If you know in advance that you will be missing class please contact me to make arrangements regarding homework.

If you understand how to do the homework problems you will have an easier time with the Exams.

Class structure:

Lectures will be the primary source of information.  Students are expected to attend every class and to participate in class discussions.  Homework assignments will be discussed in class. Students will be expected to work problems in class. You will find it beneficial to review the chapters before the lecture. 

Your laboratory work on your team design projects in the co-requisite EE231L count towards the lecture course grade as well as your Lab grade.  This is to encourage you to put in a good effort on and use of the lecture materials in your designs.

Office hours are open for discussion of anything. You can get help with homework, projects, or more detailed explanations of topics covered in class. Feel free to stop by, email me, or make an appointment to meet another time.


Class Topics and Order of Material

lWeek

Topics

Notes

HW*

Objectives

1/17

Course Introduction and Pre-Requisite Material Review (Reprise EE231 Final)

IC Amplifier Building Blocks

See BB/web for EE231
Ch. 7

7.12, 7.19, 7.21

0


1,2

1/24

IC Amplifier Building Blocks

 

Ch. 7

 

7.25, 7.31, 7.48, 7.67, 7.78

1,2

1/30

Differential and Multistage Amplifiers

Ch. 8

8.1, 8.4, 8.6, 8.14

1,2,7

2/7

Differential and Multistage Amplifiers (Cont.)

Ch. 8

8.32, 8.39, 8.40, 8.86, 8.17

1,6

2/14

Review for Exam 1

Exam 1 (Chapters 7-8)

 

 

1,2,6,7

 

2/20

2/21

President’s Day – No Classes

 (Tuesday is Monday – No Class)

 

 

 

2/28

Frequency Response
Delayed Exam 1 Reprise

Ch. 9

9.1, 9.4, 9.17, 9.33, 9.45, 9.66

6

3/7

Feedback

Ch. 10
CTMS-UMich

10.1, 10.16, 10.34, 10.35, 10.62

2, 3, 4

3/14

Spring Recess – No Classes

 

 

 

3/21

Feedback (cont.)

Ch. 10

10.80, 10.84, 10.87, 10.89, 10.95

2, 3, 4

3/28

Output Stages - Power Amplifiers

Ch. 11

11.2, 11.10, 11.16, 11.24

2, 3, 4

4/4

Output Stages - Power Amplifiers (cont.)

Review for Exam 2

Ch. 11

 

11.30, 11.32, 11.54

2, 3, 4

4/11

Exam 2 (Chapters 9-11)

Operational Amplifier Circuits

 

Ch. 12

 

12.1, 12.7, 12.16, 12.28

2, 3, 4

5

4/18

Exam 2 Reprise

CMOS Logic


Easter Recess

 

Ch. 13

 

 

12.42, 12.52, 12.56, 12.58, 12.62, 12.75


13.3, 13.10, 13.14

2, 3, 4

5

4/26

Course Review

 

 

 

1-8

May 4-11 TBD

Final Exam

(Comprehensive)

 

 

 

*Students to perform outside of class, Most answers (not solutions) are in Appendix I
** Use Multisim to confirm results