. Since the gate is
essentially an open circuit it draws no current, and the output voltage
will be equal to either ground or to the power supply voltage, depending
on which transistor is conducting.
[Diode Logic (DL)]
[Resistor-Transistor Logic (RTL)]
[Diode-Transistor Logic (DTL)]
[Transistor-Transistor Logic (TTL)]
[Emitter-Coupled Logic (ECL)]
[CMOS]
CMOS logic is a newer technology, based on the use of complementary MOS transistors to perform logic functions with almost no current required. This makes these gates very useful in battery-powered applications. The fact that they will work with supply voltages as low as 3 volts and as high as 15 volts is also very helpful.
CMOS gates are all based on the fundamental inverter circuit shown to the left. Note that both transistors are enhancement-mode MOSFETs; one N-channel with its source grounded, and one P-channel with its source connected to +V. Their gates are connected together to form the input, and their drains are connected together to form the output.
The two MOSFETs are designed to have matching characteristics. Thus,
they are complementary to each other. When off, their resistance is
effectively infinite; when on, their channel resistance is about
200 . Since the gate is
essentially an open circuit it draws no current, and the output voltage
will be equal to either ground or to the power supply voltage, depending
on which transistor is conducting.
When input A is grounded (logic 0), the N-channel MOSFET is
unbiased, and therefore has no channel enhanced within itself. It is an
open circuit, and therefore leaves the output line disconnected from
ground. At the same time, the P-channel MOSFET is forward biased, so it
has a channel enhanced within itself. This channel has a resistance of
about 200 , connecting the
output line to the +V supply. This pulls the output up to +V
(logic 1).
When input A is at +V (logic 1), the P-channel MOSFET is off and the N-channel MOSFET is on, thus pulling the output down to ground (logic 0). Thus, this circuit correctly performs logic inversion, and at the same time provides active pull-up and pull-down, according to the output state.
This concept can be expanded into NOR and NAND structures by combining inverters in a partially series, partially parallel structure. The circuit to the right is a practical example of a CMOS 2-input NOR gate.
In this circuit, if both inputs are low, both P-channel MOSFETs will be turned on, thus providing a connection to +V. Both N-channel MOSFETs will be off, so there will be no ground connection. However, if either input goes high, that P-channel MOSFET will turn off and disconnect the output from +V, while that N-channel MOSFET will turn on, thus grounding the output.
The structure can be inverted, as shown to the left. Here we have a two-input NAND gate, where a logic 0 at either input will force the output to logic 1, but it takes both inputs at logic 1 to allow the output to go to logic 0.
This structure is less limited than the bipolar equivalent would be, but there are still some practical limits. One of these is the combined resistance of the MOSFETs in series. As a result, CMOS totem poles are not made more than four inputs high. Gates with more than four inputs are built as cascading structures rather than single structures. However, the logic is still valid.
Even with this limit, the totem pole structure still causes some problems in certain applications. The pull-up and pull-down resistances at the output are never the same, and can change significantly as the inputs change state, even if the output does not change logic states. The result is uneven and unpredictable rise and fall times for the output signal. This problem was addressed, and was solved with the buffered, or B-series CMOS gates.
The technique here is to follow the actual NAND gate with a pair of inverters. Thus, the output will always be driven by a single transistor, either P-channel or N-channel. Since they are as closely matched as possible, the output resistance of the gate will always be the same, and signal behavior is therefore more predictable.
One of the main problems with CMOS gates is their speed. They cannot operate very quickly, because of their inherent input capacitance. B-series devices help to overcome these limitations to some extent, by providing uniform output current, and by switching output states more rapidly, even if the input signals are changing more slowly.
Note that we have not gone into all of the details of CMOS gate construction here. For example, to avoid damage caused by static electricity, different manufacturers developed a number of input protection circuits, to prevent input voltages from becoming too high. However, these protection circuits do not affect the logical behavior of the gates, so we will not go into the details here.
[Diode Logic (DL)]
[Resistor-Transistor Logic (RTL)]
[Diode-Transistor Logic (DTL)]
[Transistor-Transistor Logic (TTL)]
[Emitter-Coupled Logic (ECL)]
[CMOS]
Go to the Logic Family base page.