The Four-Input Multiplexer

Direct links to other logic pages:


Combinational Logic: [Basic Gates] [Derived Gates] [The XOR Function] [Binary Addition] [Multiplexer] [Decoder/Demultiplexer]
Sequential Logic: [RS NAND Latch] [Clocked RS Latch] [RS Flip-Flop] [JK Flip-Flop] [D Latch] [Flip-Flop Symbols]
Counters: [Basic 4-Bit Counter]
Registers: (Coming Soon)


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Four-input Multiplexer

The multiplexer concept is not limited to two data inputs. If we add a second addressing input, B, we can control as many as four data inputs, as shown to the left. A third and fourth addressing input will allow the multiplexer to control eight or sixteen inputs, respectively.

Please allow a little time for this interactive demonstration to load. It requires 64 separate images, each approximately 4K.

Inputs A and B are the addressing inputs to this multiplexer. They select which of the four data inputs will be transmitted to the final output, X. If the data inputs are to be multiplexed for transmission to a distant location, the inputs must cycle through all four possible addreses more than twice for each single cycle of each of the data inputs. Otherwise the input data cannot be reconstructed accurately at the receiving end.


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