Combinational Logic:
[Basic Gates]
[Derived Gates]
[The XOR Function]
[Binary Addition]
[Multiplexer]
[Decoder/Demultiplexer]
Sequential Logic:
[RS NAND Latch]
[Clocked RS Latch]
[RS Flip-Flop]
[JK Flip-Flop]
[D Latch]
[Flip-Flop Symbols]
Counters:
[Basic 4-Bit Counter]
Registers:
(Coming Soon)
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One circuit I've received a number of requests for is the multiplexer circuit. This is a digital circuit with multiple signal inputs, one of which is selected by separate address inputs to be sent to the single output. It's not easy to describe without the logic diagram, but is easy to understand when the diagram is available.
A two-input multiplexer is shown below.
A very common application for this type of circuit is found in computers, where dynamic memory uses the same address lines for both row and column addressing. A set of multiplexers is used to first select the row address to the memory, then switch to the column address. This scheme allows large amounts of memory to be incorporated into the computer while limiting the number of copper traces required to connect that memory to the rest of the computer circuitry. In such an application, this circuit is commonly called a data selector.
Multiplexers are not limited to two data inputs. If we use two addressing inputs, we can multiplex up to four data signals. With three addressing inputs, we can multiplex eight signals. If you would like to see a demonstration of a four-input multiplexer, you can follow this link. This demonstration requires 64 separate images, each approximately 4K bytes in size, so it will take a little while to load. For this reason, it is not included in the list of digital pages at the top of each page. An eight-input multiplexer would require either 2048 separate images or a rather complex implementation of dynamic HTML; therefore it will not be included on these pages.
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